Performance for the Next Generation Datacenter
With applications and workloads becoming increasingly complex, it is vital for any new hardware platform to keep up with continually increasing performance demands. Launching today, the new Intel© Xeon© Processor Scalable Family does just that with several key improvements in architecture and performance. The platform benefits greatly from a 1.5x increase in memory bandwidth and support for DDR4 2666 memory modules. In addition, the older QPI (QuickPath Interconnect) has been replaced by the new Intel© UPI (Ultra Path Interconnect) increasing speeds to 10.4 GT/s. A revised cache hierarchy boosts the amount of private L2 cache per core to reduce contention and increase performance. All of these performance enhancements coupled with up to 28 cores and 56 threads per socket make the new Pogo Linux Iris servers, powered by the new Intel© Xeon© Processor Scalable Family perfect for today and tomorrow’s most diverse and demanding data center applications.
Alongside the performance improvements, the new Iris servers also provide enhanced features focused on energy efficiency and power management. New optimized Turbo profiles mean servers can reduce clock frequencies more gradually as the number of active cores increases. This provides a better range of performance while reducing power consumption. Other advancements include dynamic power sharing between core, uncore, and MCP companion die, plus larger L2 cache for reduced interconnect and coherence activity, increasing efficiency. For power management, the processors support the new Intel© Speed Shift Technology for autonomous P-state control. This new technology increases the cooperation between hardware and software performance control, providing finer grained, faster power control changes. All of these additions and updates add up to the most power efficient Xeon© processors Intel© has ever produced.
Security is also a top priority with the new platforms. Page Protection Keys (PPK) extends the paging architecture to provide page-granular, thread-private user-level memory protection. Additionally, Mode Based Execution (MBE) protects against malicious kernel updates in a virtualized system. Also, MPX (Memory Protection Extension) enables bounds checking on data accesses to prevent buffer overflow attacks.
- 1.5x increase in memory bandwidth and support for DDR4 2666
- Up to 28 cores / 56 threads per socket
- Ultra Path Interconnect (Intel© UPI) replaces QPI (QuickPath Interconnect)
- Re-architected L2 & L3 cache hierarchy – larger private L2 cache, less shared L3
- New instruction set architecture enhancements including compute (Intel AVX-512),
virtualization (improved time stamp counter), and security (Page Protections Keys, Mode Based Execution, MPX – Memory Protection Extension)
- Energy Efficiency:
- Optimized intermediate core turbo profile
- Dynamic power-sharing between core, uncore, and MCP companion die
- Larger L2 cache reduces interconnect and coherence activity
- Power Management Enhancements:
- Intel SpeedShift Technology for autonomous P-state control
- Improved core and uncore frequency scaling heuristics
- On-die Pmax detector for rapid response to power excursions
- Newly optimized Turbo profiles enable large frequency increases
at intermediate active core counts
See the complete line of new Pogo Linux Iris Servers featuring the Intel Xeon Processor Scalable Family at: https://www.pogolinux.com/products/intel-servers